All logic gates can be created using NAND logic gates.
Creating logic gates from NAND gates is called NAND logic.
NOT Gates
Y = A NAND A
NOT From NAND Truth Table
A | Y (A NAND A) |
---|---|
0 | 1 |
1 | 0 |
AND Gates
AND gates from NAND gates are basically negated NAND gates.
Y = P0 NAND P0 = (A NAND B) NAND (A NAND B)
AND From NAND Truth Table
A | B | P0 (A NAND B) | Y (P0 NAND P0) |
---|---|---|---|
0 | 0 | 1 | 0 |
0 | 1 | 1 | 0 |
1 | 0 | 1 | 0 |
1 | 1 | 0 | 1 |
OR Gates

Y = P0 NAND P1 = (A NAND A) NAND (B NAND B)
OR From NAND Truth Table
A | B | P0 (A NAND A) | P1 (B NAND B) | Y (P0 NAND P1) |
---|---|---|---|---|
0 | 0 | 1 | 1 | 0 |
0 | 1 | 1 | 0 | 1 |
1 | 0 | 0 | 1 | 1 |
1 | 1 | 0 | 0 | 1 |
NOR Gates
NOR gates from NAND gates are basically negated OR gates.
Y = P2 NAND P2 = (P0 NAND P0) NAND (P1 NAND P1) = ((A NAND A) NAND (A NAND A)) NAND ((B NAND B) NAND (B NAND B))
NOR From NAND Truth Table
A | B | P0 (A NAND A) | P1 (B NAND B) | P2 (P0 NAND P1) | P2 (P2 NAND P2) |
---|---|---|---|---|---|
0 | 0 | 1 | 1 | 0 | 1 |
0 | 1 | 1 | 0 | 1 | 0 |
1 | 0 | 0 | 1 | 1 | 0 |
1 | 1 | 0 | 0 | 1 | 0 |
XOR Gates
Y = P1 NAND P2 = (A NAND P0) NAND (P0 NAND B) = ((A NAND (A NAND B)) NAND ((B NAND (A NAND B))
XOR From NAND Truth Table
A | B | P0 (A NAND B) | P1 (A NAND P0) | P2 (P0 NAND B) | Y (P1 NAND P2) |
---|---|---|---|---|---|
0 | 0 | 1 | 1 | 1 | 0 |
0 | 1 | 1 | 1 | 0 | 1 |
1 | 0 | 1 | 0 | 1 | 1 |
1 | 1 | 0 | 1 | 1 | 0 |
XNOR Gates
XNOR gates from NAND gates are basically negated XOR gates.
Y = P3 NAND P3 = (P1 NAND P2) NAND (P1 NAND P2) = ((A NAND P0) NAND (P0 NAND B)) NANDÂ (A NAND P0) NAND (P0 NAND B) = (((A NAND (A NAND B)) NAND ((B NAND (A NAND B)) ) NAND (((A NAND (A NAND B)) NAND ((B NAND (A NAND B)))
XNOR From NAND Truth Table
A | B | P0 (A NAND B) | P1 (A NAND P0) | P2 (P0 NAND B) | P3 (P1 NAND P2) | Y (P0 NAND P0) |
---|---|---|---|---|---|---|
0 | 0 | 1 | 1 | 1 | 0 | 1 |
0 | 1 | 1 | 1 | 0 | 1 | 0 |
1 | 0 | 1 | 0 | 1 | 1 | 0 |
1 | 1 | 0 | 1 | 1 | 0 | 1 |